In this paper the sensitivity of on-chip interconnects to Si CMOS process parameters in two different test structures are reported; two coupled lines with shielding, and without shielding. Simulations are performed using HSpiceRF to emulate the state-of-the-art and the future technologies for the test structures. Some important parameters characterizing the coupled interconnects have been examined. Shielding effectiveness on crosstalk reduction is computed using HSpiceRF simulation results in order to compare the efficiency of shielding structures with different process parameters. Additionally we investigate the influence of the process parameters in deep sub-micron technologies on the transmission, reflection, near-end, and far-end crosstalk characteristics of the coupled interconnect with and without the presence of shielding lines.